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In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (R ON,SP ) is 94 mΩmm 2 , and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (g m ) at high gate voltages, with acceptable off-state leakage current (I off ), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (f MAX ) and cutoff frequency (f T ) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

Hot carrier stress is evaluated on a laterally diffused MOSFET (LDMOS) by TCAD simulation. The device under test is obtained from process simulation under a 1µm CMOS flow available at CDTA. The n-type transistor uses the LOCOS (local oxidation of silicon) and single RESURF (reduced surface field) features. Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage VTH, ON-state resistance RON, saturation current IDsat, and device lifetime are extracted. The shifts were found to be manageable, they have a single process mechanism and are due to hot electrons in our case. But, flicker noise assessment under the same stress shows noticeable instabilities.

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This paper investigates the ruggedness of an n-type LDMOS under single shot unclamped inductive switching (UIS) stress conditions. We present a detailed method to define the electrothermal safe operating area (SOA), and the physics of the failure mechanism is described. We conclude that the device robustness depends mainly on the gate bias, much less on the pulse duration on millisecond range, the inductive load value, or the initial operating temperature, although the Kirk effect is always present under all conditions. However, the failure mechanism fundamentally changes to pure avalanche breakdown under short pulses.