A reliable factorial experimental design was applied to DRIE for specifically producing high-aspect ratio trenches. These trenches are to be used in power electronics applications such as active devices: deep trench superjunction MOSFET (DT-SJMOSFET) and passive devices: 3D integrated capacitors. Analytical expressions of the silicon etch rate, the verticality of the profiles, the selectivity of the mask and the critical loss dimension were extracted versus the process parameters. The influence of oxygen in the passivation plasma step was observed and explained. Finally, the analytical expressions were applied to the devices objectives. A perfectly vertical trench 100-lm deep was obtained for DT-SJMOSFET. Optimum conditions for reaching high-aspect ratio structures were determined in the case of high-density 3D capacitors.

Abstract:RFID solutions will improve the traceability of biological samples stored at low temperature (77K) in biobanks. To achieve this goal, the reliability of RFID tags is essential. In this paper, we focus on the reliability aspect of RFID tags in harsh environment and more specifically to assembly design optimization through numerical simulations and accelerated life tests. A packagedimensioned model and a wire-interconnect centered model have been used to assess stress distribution in the package and wire bonds. We also develop a specific versatile test bench to apply thermal cycling while monitoring the functionality of the tags. We investigate 3 different tag configurations and demonstrate that the main failure mode is related to wire breaks. The occurrence of this failure depends mainly on the nature and thickness of the encapsulant resin which induce compressive and tensile stresses during thermal cycling. FEM results are in good agreement with observed failures.