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In this paper we study algorithms for performing the LU and QR factorizations of dense matrices. Recently, two communication optimal algorithms have been introduced for distributed memory architectures, referred to as communication avoiding CALU and CAQR. In this paper we discuss two algorithms based on CAQR and CALU that are adapted to multicore architectures. They combine ideas to reduce communication from communication avoiding algorithms with asynchronism and dynamic task scheduling. For matrices that are tall and skinny, that is, they have many more rows than columns, the two algorithms outperform the corresponding algorithms from Intel MKL vendor library on a dual-socket, quad-core machine based on Intel Xeon EMT64 processor and on a four-socket, quad-core machine based on AMD Opteron processor. For these matrices, multithreaded CALU outperforms the corresponding routine dgetrf from Intel MKL library up to a factor of 2.3 and the corresponding routine dgetrf from ACML library up to a factor of 5, while multithreaded CAQR outperforms by a factor of 5.3 the corresponding dgeqrf routine from MKL library.

The class J design space is investigated with half wave current excitation for a solid‐state RF amplifier capable of delivering hundreds of watts. Unlike conventional class J designs, the present analysis aims to explore a continuous design space in order to operate a commercially available device, within its practical limits of drain voltage. This design analysis together with package effects and the inclusion of non‐linear capacitor is verified experimentally by fabricating a high‐power (550 W CW) high‐efficiency (62.8%) solid‐state amplifier operating at 505.8 MHz. This power was obtained by in‐phase combining two similar continuous class J stages, each one contributing half of the total power. For high‐power lateral diffused metal‐oxide semiconductor devices, the class J design space is found to be more realisable than popular modes of operation in view of the large non‐linear output capacitance of the device. The measured output power, efficiency, spurious response and large signal output reflection coefficients are satisfactory and as anticipated from the design analysis. Since the final application of this amplifier is for a solid‐state transmitter, a study of repeatability in terms of phase and amplitude imbalances was carried out by fabricating and evaluating multiple amplifiers, each one working with the proposed design principle.