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Verifying large industrial designs is getting harder undetected bugs? In which modules the verification team each day. The current verification methodologies are not able to should concentrate their effort? The objective of this paper is to guarantee bug free designs. Some recurrent questions during use software engineering techniques to answer these questions. a design verification are: Which modules are most likely to contain undetected bugs? In which modules the verification The novelty of this work Si to poit which hardware modules team should concentrate their effort? This information is very are most likely to have design bugs using history information useful, because it is better to start verifying the most bug-prone available in concurrent versioning systems [13], [14]. Mining modules. In this work we present a novel approach to answer software repositories to track design history changes and bug these questions. In order to identify these bug-prone modules the revision history of the design is used. Using information of re isoa w idely se te e insotre velon t.an academic experiment, we demonstrate that there is a close The iformation available i these concurrent versionig sysrelationship between bugs/changes history and future bugs. Our tems are useful to predict future bugs and to model bugs results show that allocating modules for verification based on patterns that helps reducing future bugs. bugs/changes leaded to the coverage of 91.67% of future bugs, This paper is outlined as follows. Section 2 discusses related while random based strategy covered only 37.5% of the future work mainly focused in software engineering techniques to bugs.identify bug-prone modules. In Section 3 we present the

Deadlock and nondeterminism may become increasingly hard to detect in concurrent and distributed systems. UML activity diagrams are flowcharts that model sequential and concurrent behavior. Although the UML community widely adopts such diagrams, there is no standard approach to verify the presence of deadlock and nondeterministic behavior in activity diagrams. Nondeterminism is usually neglected in the literature even though it may be considered a very relevant property. This work proposes a framework for the automatic verification of deadlock and nondeterminism in UML activity diagrams. It introduces a compositional CSP semantics for activity diagrams that is used to automatically generate CSP specifications from UML models. These specifications are the input for the automatic verification of deadlock and nondeterministic behavior using the FDR refinement checker. We propose a plugin for the Astah modeling environment that mechanizes the translation process, and that calls FDR in the background to perform the verification of properties. The tool keeps the traceability between a diagram and its CSP specification. It parses the FDR results to highlight the diagram paths that lead to a deadlock or a nondeterministic behavior. This framework adds verification capabilities to the UML modeling tool and keeps the formal semantics transparent to the users. Therefore, the user does not need to understand or manipulate formal notations during modeling. We present the results of a case study that applies the proposed framework for the verification of models in the domain of cloud computing. We discuss future applications due to the potential of our approach.

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