Low Power dissipation and smaller area are one of the important factors while designing multipliers for digital circuits. As multipliers used in digital circuits dissipate large amount of heat whenever there is a transition of bits. Reversible Logic has emerged as a promising technology in reducing power dissipation. It has application in various fields such as low power VLSI, Quantum computing and Nano-technology. Hence, In this paper we try to design a reversible multiplier using Peres gate and Full adder. We show that, proposed multiplier is efficient in terms area, power and delay. Furthermore, it requires fewer garbage outputs and constant inputs. Proposed reversible multiplier is implemented using VHDL, simulated and synthesized on Xilinx 13.1 tool.