Sphinx1 is a novel pixel architecture adapted for X-ray imaging that can detect radiation by photon counting and by charge integration. In photon counting mode, each photon is compensated by one or more counter-charge packets which can be dimensioned at a level as low as 100 electrons and the number of injected counter-charge packets indicates the incoming photon energy, thus allowing a spectrometric detection. The pixel is also able to detect radiation by integrating the charges deposited by all incoming photons and converting this analog value into a digital data with a least significant bit (LSB) of 100 electrons through the use of the counter-charge concept. In this paper, Sphinx1 pixel architecture is presented with emphasis on the counter-charge design, and the two modes of operation are described in detail. The pixel was simulated using Eldo simulator. Simulation results indicate an equivalent noise charge (ENC) of 48 electrons-rms for a detector capacitance of 75 fF. The LSB linearity and the ENC are further studied for different values of detector capacitances. The analog and digital power consumptions are calculated to be less than W in static conditions, proving the architecture to be suitable for large area detectors. Finally, corner simulations show a consistent performance against transistors mismatch. Proof of concept test chip of mm mm. test chip is being designed fabricated in CMOS m technology, with a pixel pitch of m.

Sphinx1 is a novel pixel architecture adapted for X-ray imaging, it detects radiation by photon counting and charge integration. In photon counting mode, each photon is compensated by one or more counter-charges typically consisting of 100 electrons (e-) each. The number of counter-charges required gives a measure of the incoming photon energy, thus allowing spectrometric detection. Pixels can also detect radiation by integrating the charges deposited by all incoming photons during one image frame and converting this analog value into a digital response with a 100 electrons least significant bit (LSB), based on the counter-charge concept. A proof of concept test chip measuring 5 mm × 5 mm, with 200 μm × 200 μm pixels has been produced and characterized. This paper provides details on the architecture and the counter-charge design; it also describes the two modes of operation: photon counting and charge integration. The first performance measurements for this test chip are presented. Noise was found to be ∼80 e-rms in photon counting mode with a power consumption of only 0.9 μW/pixel for the static analog part and 0.3 μW/pixel for the static digital part.