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A metal–oxide–semiconductor (MOS) gate stack that is self-aligned with the underlying silicon doping profile is demonstrated. We combine a new hybrid bottom-up patterning technique with atomic layer deposition (ALD) to selectively deposit a platinum-hafnium dioxide-silicon MOS gate stack. A poly(methyl methacrylate) (PMMA) brush is blanket grown from a Si(100) surface and selectively removed from the lightly doped (∼1018 cm−3) regions using a doping-selective KOH etch. The PMMA brush that remains on the heavily doped (∼1020 cm−3) regions effectively blocks the ALD of both HfO2 and platinum. MOS capacitors exhibit promising capacitance-voltage characteristics with a HfO2 dielectric constant of ∼25 and an average interface state density of 2.1 × 1011 eV−1 cm−2 following forming gas anneal.

We demonstrate a bottom-up process for programming the deposition of coaxial thin films aligned to the underlying dopant profile of semiconductor nanowires. Our process synergistically combines three distinct methods – vapor-liquid-solid (VLS) nanowire growth, selective coaxial lithography via etching of surfaces (SCALES), and area-selective atomic layer deposition (AS-ALD) – into a cohesive whole. Here, we study ZrO2 on Si nanowires as a model system. Si nanowires are first grown with an axially modulated n-Si/i-Si dopant profile. SCALES then yields coaxial poly(methyl methacrylate) (PMMA) masks on the n-Si regions. Subsequent AS-ALD of ZrO2 occurs on the exposed i-Si regions and not on those masked by PMMA. We show the spatial relationship between nanowire dopant profile, PMMA masks, and ZrO2 films, confirming the programmability of the process. The nanoscale resolution of our process coupled with the plethora of available AS-ALD chemistries promises a range of future opportunities to generate structurally complex nanoscale materials and electronic devices using entirely bottom-up methods.

Self-aligned metal-oxide-semiconductor (MOS) capacitors are studied with several low-temperature, wet chemical silicon dioxide (SiO2) interlayers to understand their impact on electrical performance. Self-aligned MOS capacitors are fabricated with a bottom-up patterning technique that uses a poly(methyl methacrylate) brush and dopant-selective KOH etch combined with area-selective atomic layer deposition of hafnium dioxide (HfO2) and Pt. The wet chemical pretreatments used to form the SiO2 interlayer include hydrofluoric acid (HF) etch, 80 °C H2O, and SC-2. Capacitance-voltage measurements of these area-selective capacitors exhibit a HfO2 dielectric constant of ∼19, irrespective of pretreatment. After a forming gas anneal, the average interface state density decreased between 1.8 and 7.5 times. The minimum observed Dit is 1 × 1011 eV−1 cm−2 for the HF-last treatment. X-ray photoelectron spectroscopy shows an increase in stoichiometric SiO2 in the interfacial layer after the anneal. Additional carbon is also observed; however, comparison with capacitors fabricated in a nonselective process reveals minimal impact on performance.