Abstract-Median filters are a popular method for noise extraction, with much work done in the community to achieve high throughput and low hardware cost. In contrast, energy efficiency remains an untapped area for improvement though it has become a topic of increasing interest. We deduce memory to be the main contributing factor through energy consumption analysis of our median filter architecture. To lower memory energy demands, we use a memory activation scheduling technique, developing an optimal schedule for memory blocks and enabling the minimum number of blocks required each cycle, while deactivating the other blocks. We implement our median filter architecture on a state-of-the-art FPGA to evaluate the performance, using image sizes from 128 × 128 to 1024 × 1024 pixels with standard pixel depths of 8 bpp, 16 bpp, 24 bpp and 32 bpp. Our implementation has up to 53% of the peak performance of the target device. The post place-and-route results show that our energy-optimized median filter implementation has an average of 4.0× higher energy efficiency in comparison with the baseline architecture with fully-enabled memory and can maintain at least 400 frames/s for a 512 × 512 image for any pixel depth.

Packet classification is used in network firewalls to identify and filter threats or unauthorized network access at the application level. This is realized by comparing incoming packet headers against a predefined ruleset. Many solutions to packet classification are available, but most of these solutions exploit some features of the ruleset in order to minimize the memory footprint of ruleset storage. However, when the expected ruleset features are not present, feature-reliant solutions may yield poor memory efficiency. In this paper, we focus on two ruleset independent packet classification schemes, Ternary Content Addressable Memory (TCAM), a brute force search method, and StrideBV, a bit-vector-based algorithmic solution, to determine which solution is more suited for high performance packet classification. Using ruleset sizes ranging from 32 to 2048 (targeted for firewall rulesets), we implement both schemes on a Field-Programmable Gate Array (FPGA) to evaluate their performance. We measure the performance using memory efficiency, resource consumption, throughput and power efficiency metrics for both solutions. The post place-and-route results on a state-of-the-art FPGA reveal that StrideBV has 4.5× and 3.5× higher power efficiency in comparison with TCAM, along with 6× and 4× higher throughput when using distributed RAM and block RAM as memory respectively. TCAM has better memory efficiency, though its improvement over StrideBV varies.

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The construction of histograms is an integral part of image processing pipelines, useful for image editing features such as histogram matching, thresholding and histogram equalization. In the past, research done on kernels used in image processing pipelines target advancements to achieve high throughput, area efficiency and low cost. However, a growing topic of interest that has not been fully explored is the use of energy efficiency as a key metric. In this work, we focus on developing an energyefficient histogram implementation with a minimum frame rate of at least 30 frames per second. We determine the components that consume the most power and propose an optimized histogram implementation with the utilization of multiple optimizations to achieve notable improvement in energy efficiency while maintaining suitable throughput for usage within image processing pipelines. These optimizations include a data-defined memory activation schedule, a careful data layout and circuit-level pipelining. Our architecture is implemented on commonly-used image sizes which vary from 240×128 to 1216×912 and assume a pixel width of 16 bits per pixel. The post place-and-route results show that our optimized architecture has up to 15.3× higher energy efficiency when compared against the baseline architecture.