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A regression analysis of competitors' tournament results in relation to their world rankings was proposed to identify the effect of home advantage in international 'grand-slam' tennis and 'major' golf tournaments. The results provided little evidence of home advantage in either the grand-slam tennis or the golf tournaments held in 1993. The only possible evidence of home advantage was found in the Wimbledon tennis and the US Open golf championships. Even these findings can be explained, at least partially, by (1) the availability of information concerning the low world rankings of the British tennis players competing at Wimbledon, and (2) selective entry, allowing only the world's top-ranked foreign golfers into the US open golf tournament. In both cases, the lower ranking home competitors have a greater opportunity to perform above their anticipated world rankings. Therefore, provided entry into tennis and golf tournaments is truly 'open' to both the host nation's representatives and foreign competitors alike, home advantage does not appear to be a major factor influencing the competitors' performance in such competitions. These findings may be explained by the relatively objective nature of the scoring systems used in tennis and golf, unlike the subjective influence of refereeing decisions on the results of team-games such as soccer.

SPA is a synthesised, self-timed, ARM-compatible processor core. The use of synthesis was mandated by a need for rapid implementation. This has proved to be very effective, albeit with increased cost in terms of area and performance compared with earlier non-synthesised processors. SPA is employed in an experimental smartcard chip which is being designed to evaluate the applicability of self-timed logic in security-sensitive devices. The Balsa synthesis system is used to generate dual-rail logic with some enhancements to improve security against non-invasive attacks. A complete system-on-chip is being synthesised with a only small amount of hand design being employed to boost the throughput of the on-chip interconnection system.

A silicon compiler, Balsa-c, has been developed for the automatic synthesis of asynchronous, delay-insensitive circuits from the language Balsa. Balsa is derived from CSP with similar language constructs and a single-bit granularity type system. Balsa compiles to intermediate handshake circuits by an extended form of the compilation function used in the Tangram system.The handshake circuits are subsequently mapped to CMOS implementations of 4-phase bundled-data asynchronous circuits by a suite of parameterised component-generating scripts within the Cadence design framework.