Rational use of novel high‐performance semiconductors in field‐effect transistors (FETs) requires exact knowledge of the dominating charge transport mechanisms. In particular, the distinction between contact‐ and semiconductor‐limited transport is important in FETs with small channel lengths. Here, we analyze the relative contributions of contact limitation and intrinsic conductivity of FETs based on mechanically exfoliated multilayers of the high performance n‐type semiconductor molybdenum disulfide (MoS2). Based on a lithography‐free fabrication process, we realize FETs with room temperature mobility (μ) of up to 46.8 cm2/Vs and ION/IOFF ratio of up to 105. Using temperature‐ and bias‐dependent charge transport measurements, we are able to show that the intrinsic bulk transport in the flake can be best described by a phonon‐limited band transport model with a conductive bulk at room temperature that freezes out upon cooling of the sample. In addition, we notice an increase of μ by a factor of 2–5 when using a self‐assembled monolayer (SAM)‐modified SiO2/MoS2 interface. More importantly, we show that the choice of drain–source bias (VDS) is crucial when interpreting MoS2 transport measurements, while for large VDS the intrinsic semiconductor transport properties can be observed, a strong contact limitation appears at low VDS. Our combined measurements allow us to distinguish between the effect of bulk and semiconductor/dielectric interface transport and the effect of contact resistance on the electrical transport properties.