This paper deals with investigation and fabrication of 4H-SiC MOSFETs with a high-k dielectric close to ZrSiO4. We are looking for the optimal stochiometry in order to obtain full benefits of its large bandgap, a k value higher than that of SiO2, thermodynamic stability on SiC, a good interface quality and process compatibility with SiC technology. Several Si/Zr ratios have been tested with the purpose of obtaining the most favorable dielectric configuration. The first test devices have been manufactured successfully with a stack gate dielectric consisting of a thin SiO2interlayer and a ZrxSiyOz(theoretical Si/Z=0.7) layer on top.
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