Abstract-Evolvable hardware (EH) is an interesting alternative to conventional digital circuit design, since autonomous generation of solutions for a given task permits selfadaptivity of the system to changing environments, and they present inherent fault tolerance when evolution is intrinsically performed. Systems based on FPGAs that use Dynamic and Partial Reconfiguration (DPR) for evolving the circuit are an example. Also, thanks to DPR, these systems can be provided with scalability, a feature that allows a system to change the number of allocated resources at run-time in order to vary some feature, such as performance. The combination of both aspects leads to scalable evolvable hardware (SEH), which changes in size as an extra degree of freedom when trying to achieve the optimal solution by means of evolution. The main contributions of this paper are an architecture of a scalable and evolvable hardware processing array system, some preliminary evolution strategies which take scalability into consideration, and to show in the experimental results the benefits of combined evolution and scalability. A digital image filtering application is used as use case.

Abstract-In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

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Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications. The RC architecture is based on a two dimensional meshtype systolic array of Processing Elements (PEs). EachPE is a basic computational unit (occupying just 5 CLBs) able to perform a single operation per clock cycle, with the data taken from their close neighbors. Each PE includes a Functional Block that performs a basic operation with one or two input signals (North and West), and sends the result through two outputs (South and East). With DPR the PEs can be changed at runtime, and as an extension of previous systems shown in [1], also the surrounding elements (input multiplexors and output selector) are reconfigurable. This allows the array to scale up or down as desired, obtaining more or less processing resources according to the needs.Another feature of the system is self-adaptivity to the different conditions in the type and level of noise, and fault tolerance due to the usage of the same hardware in both the evolution stage and the filtering stage. This fault tolerance was described in [2], showing the self-healing capability of recovering from many permanent accumulated faults. This can be achieved by injecting a fault to emulate a damaged PE.A special usage of the real time images obtained from the camera is shown in Figure 2. The system includes a noise generator that emulates different types and levels of noise to be filtered, adding it to the images taken from the camera. With this emulator, evolution with real time images can be carried out. Furthermore, the possibility of evolving with two consecutive noisy frames is shown, obtaining results comparable to the ones obtained by traditional evolution, with the advantage of adapting to whichever conditions of noise type and level the input images have, rather than depending on previously stored training images for a pre-characterized noise type and level.The combination of EH and scalability yields better results than any of our previously published results.Figure 2. Screenshot demonstrating evolution based on two consecutive camera noisy frames REFERENCES Otero, A.; Salvador, R.; Mora, J.; de la Torre, E.; Riesgo, T.; Sekanina, L.; , "A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive...

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