In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.Index Terms-Low bit-depth motion estimation, motion estimation hardware, source pixel based linear arrays.
In this work, a high dynamic range (HDR) image generation method using a single input image is presented. The proposed approach generates over-and under-exposed images by making use of a novel adaptive histogram separation scheme. Thus, it becomes possible to eliminate ghosting effects which generally occur when several input image containing camera/object motion are utilized in HDR imaging. Additionally, it is proposed to utilize a fuzzy logic based approach at the fusion stage which takes visibility of the inputs pixels into account. Since the proposed approach is computationally light-weight, it is possible to implement it on mobile devices such as smart phones and compact cameras. Experimental results show that the proposed approach is able to provide ghost-free and improved HDR performance compared to the existing methods 1 .
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