This paper presents an implementation of an alldigital transmitter architecture for software defined radio (SDR) applications. This transmitter uses a first order, sigma-delta modulator for one-bit quantization and noise shaping. The binary signal is passed through high-speed multiplexing circuits for frequency upconvertion directly from base-band to the desired carrier frequency [1]. This digital implementation has interesting features such as reconfigurability as well as preserving a good signal quality, at an additional expense of the high speed components required to perform oversampling and multiplexing. The behavior of the all-digital transmitter is simulated and measured using a baseband signal having 1.94 MHz bandwidth up-converted to 2.5 GHz carrier frequency. The implementation steps are shown along with the obtained simulation and measurement results. The overall linearity performance are given in terms of gain response, signal-to-noiseand-distortion ratio (SNDR) and the adjacent-channel-power ratio (ACPR).Index Terms-All-digital sigma-delta modulator, FPGA implementation, High frequency multiplexing.

In this paper, a dual-branch topology driven by a Delta-Sigma Modulator (DSM) with a complex quantizer, also known as the Complex Delta Sigma Modulator (CxDSM), with a 3-level quantized output signal is proposed. By de-multiplexing the 3-level Delta-Sigma-quantized signal into two bi-level streams, an efficiency enhancement over the operational frequency range is achieved. The de-multiplexed signals drive a dual-branch amplification block composed of two switch-mode back-to-back power amplifiers working at peak power. A signal processing technique known as quantization noise reduction with In-band Filtering (QNRIF) is applied to each of the de-multiplexed streams to boost the overall performances; particularly the Adjacent Channel Leakage Ratio (ACLR). After amplification, the two branches are combined using a non-isolated combiner, preserving the efficiency of the transmitter. A comprehensive study on the operation of this topology and signal characteristics used to drive the dual-branch Switch-Mode Power Amplifiers (SMPAs) was established. Moreover, this work proposes a highly efficient design of the amplification block based on a back-to-back power topology performing a dynamic load modulation exploiting the non-overlapping properties of the de-multiplexed Complex DSM signal. For experimental validation, the proposed de-multiplexed 3-level Delta-Sigma topology was implemented on the BEEcube™ platform followed by the back-to-back Class-E switch-mode power amplification block. The full transceiver is assessed using a 4th-Generation mobile communications standard LTE (Long Term Evolution) standard 1.4 MHz signal with a peak to average power ratio (PAPR) of 8 dB. The dual-branch topology exhibited a good linearity and a coding efficiency of the transmitter chain higher than 72% across the band of frequency from 1.8 GHz to 2.7 GHz.

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