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In this paper we provide an approach for the formal verification of a frequency domain equalizer using higher-order logic based theorem proving. We perform a multi-level formal error analysis to verify an implementation of the equalizer based on the Fast LMS (Least Mean Square) algorithm. The formal error analysis is performed at the floating-point, fixed-point, and real numbers domains. The expressiveness of higher-order logic allows us to model the equalizer in all the three number domains and valuate the errors generated by approximating the floatingand fixed-point designs to the real domain of the frequency domain equalizer. This application shows the efficiency of formal methods in analyzing and verifying complex systems such as the frequency domain equalizer.

This paper presents performance evaluation of two implementations of an equalizer: a time domain equalizer (TDE) based on the Least Mean Squares (LMS) algorithm and a frequency domain equalizer (FDE) based on the Fast LMS algorithm. The comparison between the two algorithms is based on the computational complexity and resources. The computational complexity of the two algorithms is analyzed by simulation of the TDE and FDE at at two levels of abstraction: the design specification based on floating point arithmetics using Simulink, and the design implementation based on fixed point arithmetics using Xilinx's System Generator tool. The models are used to measure both floating-point and fixed-point signal-to-noise ratio (SNR) errors based on the two algorithms and provide error estimation for the design specification and design implementation. We analyze the resources used in the implementation of the two algorithms by providing FPGA implementations in SystemGenerator. Our analysis shows that the FDE is more efficient in terms of computational complexity and resources.

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