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In this paper we show that it is possible to derive a sequential circuit either from a transition table or from a State Transition Graph (STG), so that the sequential circuit has the short test detecting all multiple stuck-at faults at gate poles of the circuit, and delay of each circuit path is detectable Keywords: finite state machine (FSM); state transition graph (STG); path delay faults (PDFs); multiple stuck-at faults; monotonous functions.Under development of nanometer technologies it is not enough to test single stuck-at faults at gate poles of logical circuits. We need to test multiple stuck-at faults at gate poles along with delay faults of circuits. A path delay fault (PDF) model is often used at delay testing. In accordance with the conditions of fault manifestation, PDFs are divided into robust testable faults and non-robust testable faults [1, 2]. The PDF is robust testable on condition that the fault manifestation on a test pair does not depend on delays of other circuit paths. The PDF is non-robust testable if the fault manifestation is possible only when all other paths of a circuit are faultfree. Note that the robust testable PDF may be located and measured.It is known that even for a simple circuit it is impossible to enumerate its multiple stuck-at faults, and only 20% of PDFs are robust testable. That is why it is very important to provide testability of logical circuits both for multiple stuck-at faults and delays during the circuit design.Application of these synthesis methods to a combinational part of a sequential circuit may generate rather long paths in the obtained circuit. We suggest [4] a new method of the fully delay testable combinational part design that is oriented to cutting down the lengths of circuit paths in contrast to the lengths in the circuits obtained by the method suggested in [3]. In this method [4] the circuit behavior is represented with a composition of ROBDDs and monotonous products extracted from a state transition graph (STG). The experimental results have shown that the circuit paths in the resulted combinational parts [4] are cut from two to twenty times. Unfortunately, for these circuits we cannot find rather a short test detecting all multiple stuck-at faults at their gate poles.For a high performance circuit it is desirable to detect multiple stuck-at faults together with PDFs. In paper [5] it is shown that if we apply the multilevel logic minimization method, based on algebraic division, to the system of irredundant sum of products (SoPs) describing the circuit behavior, we get a circuit testable for multiple stuck-at faults. We mean that a test detecting single faults of the literals of the system of irredundant SoPs detects all multiple stuck-at faults at gate poles of the resulted circuit.In this paper we suggest the design method that allows deriving the sequential circuit that is both fully delay testable and multiple stuck-at fault testable.The circuit behavior is represented either with a transition table or with the STG in which symbols of input a...