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This paper presents the analytical solution in time domain for the ideal single-ended Class-E Power Amplifier (PA). Based on the analytical solution a coherent non-iterative procedure for choosing the circuit parameters is presented for Class-E PA's with arbitrary duty-cycle and finite dc-feed inductance (e.g. continuously ranging from Class-E with small finite drain inductance to Class-E with RF choke). The obtained analysis results link all known Class-E PA design equations as well as presenting new design equations. The result of the analysis gives more degrees of freedom to designers in their design and optimization by further expanding the design space of Class-E PA.

A latch-type comparator with a dynamic bias preamplifier is implemented in a 65nm CMOS process. The dynamic bias with a tail capacitor is simple to implement and ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator is analyzed and compared to its prior-art in terms of energy consumption and input referred noise voltage. First-order equations are presented that show how to optimize the pre-amplifier for low noise and high gain. Both the dynamic bias comparator and the prior-art are implemented on the same die and measurements show that the dynamic bias can reduce the average energy consumption by about a factor 2.5 for the same input-equivalent noise at an input common mode level of half the supply voltage.

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, lowpower IC's that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 W; the die area is 0.063 mm 2 in a standard digital 0.35-m CMOS process. The second bandgap reference circuit aims at highaccuracy operation ( = = =0:3%) without trimming. It consumes approximately 5 W from a 1.8-V supply voltage and occupies 0.06 mm 2 in a standard 0.35-m CMOS process.

Abstract:A 9-bit 11GS/s DAC is presented that achieves an SFDR of more than 50dB across Nyquist and IM3 below -50dBc across Nyquist. The DAC uses a two-times interleaved architecture to suppress spurs that typically limit DAC performance. Despite requiring two current-steering DACs for the interleaved architecture, the relative low demands on performance of these subDACs imply that they can be implemented in an area and power efficient way. Together with a quad-switching architecture to decrease demands on the power supply and bias generation and employing the multiplexer switches in triode, the total core area is only 0.04mm 2 while consuming 110mW from a single 1.0V supply.