This paper proposes the design of tunable dual-band filters for multi-band multi-standard systems. The main objective is to provide frequency tunability in the second band while maintaining the first band fixed. To this end, the capacitive-loaded stepped-impedance resonator is used. The work is divided into two main parts. In the first part, a deep analysis of the capacitive-loaded stepped-impedance resonator structure is done, which provides analytical closed-form design equations which eases their design in front of the several approaches available in the literature up to now. The analysis is also particularized for the case of the capacitive-loaded uniform resonator. In the second part, resonators are integrated in two dual-band tunable filters.

Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of Power Delivery Networks (PDNs). Ring Oscillators Clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise as technology scales down and power density increases. However, their effectiveness highly depends on the design parameters of the PDN, power consumption patterns of the system and spatial locality of the ROCs within the clock domains. This paper analyzes the impact of the PDN parameters and ROC location on the robustness to voltage noise. The capability of reacting instantaneously to unpredictable voltage droops makes ROCs an attractive solution, which allows to reduce the amount of decoupling capacitance without downgrading performance. Tolerance to voltage noise and related benefits can be increased by using multiple ROCs and reducing the size of the clock domains. The analysis shows that up to 83% of the margins for voltage noise and up to 27% of the leakage power can be reduced by using local ROCs.

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