Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly's own Twill compiler, created by Doug Gallatin last year. Twill's original partitioning algorithm is chosen along with two other partitioning algorithms: Tabu Search + Simulated Annealing (TSSA) and Genetic Search (GS). These algorithms are implemented inside Twill and test bench input code from the CHStone HLS Benchmark tests is used as stimulus. Along with the algorithms cost models, one key attribute of interest is queue counts generated, as the more cuts between hardware and software requires queues to pass the data between partition crossings. These high communication costs can end up damaging the heterogeneous solution's performance. The Genetic, TSSA, and Twill's original partitioning algorithm are all scored against each other's cost models as well, combining the fitness and performance cost models with queue counts to evaluate each partitioning algorithm. The solutions generated by TSSA are rated as better by both the cost model for the TSSA algorithm and the cost model for the Genetic algorithm while producing low queue counts. v ACKNOWLEDGMENTS Through the five years I've spent at Cal Poly I have countless people to thank. Firstly, Iwant to thank Dr. Danowitz for taking me under as one of his first graduate students and Dr. Oliver for pointing me towards the master's degree. Also I would like to thank Toby

Recently there have been a slew of digital design products released that promise to simplify the task of giving students a real-world System-on-Chip (SoC) design experience. These "programmable SoCs" from companies such as Xilinx, Cypress, and Altera combine modern multi-core ARM processors connected to an FPGA through a widely used SoC interconnect standard. This paper discusses a Real Time Embedded System Course I designed that uses the Xilinx Zynq platform to give students first-hand experience with modern System-on-Chip design methodologies and the challenges that designers face in both hardware and software bring-up for a modern IP-based design.The first portion of this paper discusses how students were trained to use the Zynq platform. The first weeks of the class were dedicated to teaching students the basics of real-time system and custom hardware design. Students used a Zynq-based port of Free-RTOS to learn about Realtime operating systems. Through a series of laboratory assignments, students are taught how to interface the RTOS with custom hardware that they place on the FPGA portion of the chip. The course material developed for this portion of the class will be posted online so that other educators may use it in their teaching.The second part of this paper discusses some of the projects proposed and completed by students, and any difficulties the students faced along the way. From two weeks into the class, students are asked to form groups of up to four and propose a final project. For their final project, students are required to design and build a complete working system of their choice. Their final project is required to make use of both the processor running RTOS and at least one custom IP block running on the FPGA.In the final section of this paper I examine student feedback for the course, and comment on some of the challenges I faced in integrating the Zynq PSoC platform, and its corresponding development tools, into the classroom.