Routing is a key stage for VLSI physical design. Steiner tree construction is a well studied topic in design automation. There have been a number of significant theoretical advances in the past few years. The focus of this paper is on combining the speed and solution quality of a high quality Steiner heuristic with the reality of modern routing. Practical designs contain routing congestion and blockages; routing is implemented across multiple layers. Each routing layer has preferred directions, and connecting vias have significant cost. In a modern design, many trees are in competition with each other for scarce routing resources. The objective is not to simply build trees with the lowest length; they must also be low cost. We present an approach that is as fast as spanning tree construction, while accurately modeling routing costs. Our work extends an earlier Steiner tree heuristic algorithm by adding the ability to minimize the routing congestion without altering the computational complexity of the underlying algorithm. We compare our CAST algorithm with the capacitated minimum spanning tree (CMST) and the ER algorithm finding that our approach offers impressive reduction in congestion cost in average about 23.1% and 63.4%, respectively.

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Nowadays, very large scale integrated (VLSI) circuit technology is developing rapidly. It is necessary to consider many factors related to the VLSI circuit design. Interference is one of the factors that must be considered in high-frequency systems. The parasitic elements become serious limiting factors in the circuit. This research provided a method to reduce crosstalk energy by considering the transition of the signal. Crosstalk is the main capacitive effect which is elected by a high-coupling capacitance between lines. This study considers the wiring path signal with disturbance using the theory of optimization model, assisting in the search of the best sort in signal lines. The technique of a shuffled frog leaping algorithm (SFLA) is being used to search for the best value in arranged signal lines. The result will be minimal noise. The study finds that the arrangement using the SFLA causes only 36.42% of the noise. It was initially evident and 13.06%, when compared with the average all, is born noise value. These techniques can be applied in the design of arranging signal line in the VLSI circuits.