No abstract

We consider a memory device that is printed by double patterning (litho-etch-litho-etch) technology wherein positive images of ¼-pitch lines are printed in each patterning step. We analyze the errors that affect the width of the spaces. We propose a graphical method of visualizing the many-dimensional process-window for double patterning. Controlling the space-width to 10% of half-pitch is not possible under the worst combination of errors. Statistical analysis shows that overlay and etch bias are the most significant contributors to the variability of spaces. 3 [space-width] = 17% and 11% of nominal space can be achieved for 3 [Overlay] = 6 nm and 3 nm, respectively, for a 40-nm half pitch array printed using NA=0.93.

No abstract

No abstract

We present a full-chip implementation of model-based process and proximity compensation. Etch corrections are applied according to a two-dimensional model. Lithography is compensated by optimizing a cost function that expresses the design intent. The cost function penalizes edge placement errors at best dose and defocus as well as displacement of the edges in response to a specified change in a process parameter. This increases immunity to bridging in low contrast areas.