A low power method of clock signal duty cycle adjustment is presented in this paper. The proposed architecture produces a synchronous signal in the output of system with 50±1% duty cycle over PVT, which is needed to avoid data error and setup/hold time margins violations during farther operation with data. Method also helps to improve noise immunity, because in case of 50% duty cycle signal in the input of synchronous system makes it more noise protected and helps to avoid phase errors between control signals. The presented correction mechanism can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB) and some structures of ADC/DACs.

A method of serial links output data and clock signals setup and hold times correction presented in this paper. The proposed architecture produces corrected clock which have enough setup/hold time margins respect data signal over PVT, which is needed to avoid data errors and setup/hold violations during further operation with data. The presented correction mechanism can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.

No abstract

No abstract