RSA cryptographic algorithm used to encrypt and decrypt the messages to send it over the secure transmission channel like internet.  The RSA algorithm is a secure, high quality, public key algorithm. In this paper, a new architecture and modeling has been proposed for RSA public key algorithm, the suggested system uses 1024-bit RSA encryption/decryption for restricted system. The system uses the multiply and square algorithm to perform modular operation. The design has been described by VHDL and simulated by using Xilinx ISE 12.2 tool. The architectures have been implemented on reconfigurable platforms FPGAs. Accomplishment when implemented on Xilinx_Spartan3 (device XC3S50, package PG208, speed -4) which confirms that the proposed architectures have minimum hardware resource, where only 29% of the chip resources are used for RSA algorithm design with realizable operating clock frequency of 68.573 MHz.

Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can be used in several applications. Increasing use of images in industrial process therefore it is essential to protect the confidential image data from unauthorized access. Advanced Encryption Standard (AES) is a well- known block cipher that has many benefits in data encryption process.  In this paper, proposed some modification to the Advanced Encryption Standard (M-AES) to increase and reaching high level security and enhance image encryption. The modification is done by modifying the ShiftRow Transformation. Detailed results in terms of security analysis and implementation are given. Comparing the proposed algorithm with the original AES encryption algorithm shows that the proposed M-AES has more security from the cryptographic view and gives better result of security against statistical attack.