Recent works on fake news detection have shown the efficacy of using emotions as a feature or emotions-based features for improved performance. However, the impact of these emotion-guided features for fake news detection in cross-domain settings, where we face the problem of domain shift, is still largely unexplored. In this work, we evaluate the impact of emotion-guided features for cross-domain fake news detection, and further propose an emotion-guided, domain-adaptive approach using adversarial learning. We prove the efficacy of emotion-guided models in cross-domain settings for various combinations of source and target datasets from FakeNewsAMT, Celeb, Politifact and Gossipcop datasets.

Social media, blogs, and online articles are instant sources of news for internet users globally. But due to their unmoderated nature, a significant percentage of these texts are fake news or rumors. Their deceptive nature and ability to propagate instantly can have an adverse effect on society. In this work, we hypothesize that legitimacy of news has a correlation with its emotion, and propose a multi-task framework predicting both the emotion and legitimacy of news. Experimental results verify that our multi-task models outperform their single-task counterparts in terms of accuracy.

This paper presents a method to implement time optimization of instructions in Field Programmable Gate Array (FPGA) using application of embedded systems. The proposed technique is intended to reduce the time of processing of instructions inside a processor and ATMega328 microcontroller is used for this purpose. An algorithm has been proposed to predict the most suitable processor architecture which should be preferably used to iteratively execute the instructions. This prediction, along with the input of instructions to the FPGA, is done by the microcontroller and the same is transferred to the FPGA using suitable interfacing technique. Two architectures are intertwined and burnt on the microprocessor chip of the FPGA beforehand. Proteus VSM has been used for simulation of the embedded portion of the system and the processor architectures are designed in Xilinx ISE v13.4 and simulated in ISIM simulator.

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