The work in this paper is focused on designing a NBTI tolerant 6T SRAM cell while maintaining low power operation. We explore the usefulness of switched capacitor circuit to provide NBTI tolerance while reducing overall power consumption. A thorough analysis of the 6T SRAM cell has been done to show the reduction in power consumption of the cell without degrading the read and write stability. The results obtained in proposed technique are compared and contrasted with reported data for the validation of our approach. The proposed technique reduces read power by 32%, write power by 15% and leakage power by 14%. The applied technique effectively reduces overall current by considerable amount and also significant reduction in Vth degradation due to NBTI is observed hence it is suitable for NBTI tolerant low power 6T SRAM cell design.