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In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starting from an informal UML specification until getting to an RTL modeled in Verilog. We integrate the verification of the LA-Interface in the design flow by considering two intermediate levels: (1) Abstract State Machines (ASM); and (2) SystemC. The first one serves the verification by model checking of a set of PSL properties, while the second includes a set of assertions to be verified by simulation.To evaluate the performance of our approach, we used the RuleBase model checker to verify the same properties; and the OVL library to verify the same assertions.

Severe mental illness (SMI) includes schizophrenia and related conditions, bipolar disorder, and moderate and severe depression, which in total affect more than 4% of the adult population worldwide and lead to substantial premature deaths, as people with SMI die on average one to two decades earlier than the general population. 1 Since the 1950s, institutionalization or hospital care for patients with SMI has been thought to be harmful, traumatizing, and uprooting from the patient's natural environment. 2 In contrast, community-based care or intensive case management models are advocated by a number of mental health practitioners to facilitate recovery of patients from SMI. 2,3 In December 2016 and November 2017, a series of Asia-Pacific Expert Forums were organized by the Hong Kong Association of Psychosocial Rehabilitation, with the aim to review the current landscape and key challenges of the management of SMI in parts of the region,

In this paper a formal verification of the Look-Aside Interface using MDG-based model checking technique is presented. MDGs (Multiway Decision Graphs) are an extension of BDD-like data structures with a distinction of concrete sorts and abstract sorts. The Look-Aside Interface is a memory-mapped interface, targeted at devices that offload certain tasks from a network processing unit. A synthesizable RTL model in Verilog has been developed from the standard specification of the Look-Aside Interface with the design properties specified in a CTL-like specification language called LMDG. An MDG model was also built in MDG-HDL language, a Prolog-style hardware description language, from the RTL model. Finally LMDG properties were checked against the MDG-HDL model in the MDG model checker. Through our experiments, we showed a practical example of a full formal verification using MDGs.

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