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This work targets the design of a multiplexer in multilayer QCA (Quantum-dot Cellular Automata) framework. The proposed multiplexer satisfies the requirement of high device density as well as computing power. The impact of different design constraints, such as layer spacing, radius of induced effect and the size of QCA cell on logic synthesis in multilayer environment are thoroughly investigated. High level synthesis of digital design using the proposed multiplexer is explored that establishes the significant improvement in digital design with the layered structure over that of conventional design approaches.

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Non-volatile memories (NVMs) such as Spin-Transfer Torque RAM (STTRAM) have drawn significant attention due to complete elimination of bitcell leakage. In addition to the plethora of benefits such as density, non-volatility, low-power and high speed, majority of Non-Volatile Memories (NVMs) are also compatible with CMOS technology enabling easy integration. Although promising, NVM brings new security challenges that were absent in their conventional volatile memory counterparts such as Static RAM (SRAM) and embedded Dynamic RAM (eDRAM). The root cause is persistent data that may allow the adversary to retrieve sensitive information like password or cryptographic keys. This is primarily due to the fundamental dependency of these memory technologies on environmental parameters such as magnetic fields and temperature which can be exploited by the adversary to tamper with the stored data. This paper investigates the data security and privacy challenges in NVMs by exploring the security specific properties and novel security primitives realized using spintronic building blocks. A thorough analysis is done on the vulnerabilities, data security and privacy issues, threats and possible countermeasures to enable safe computing environment using spintronics.