Abstract-In this paper, an analytical noise calculation is presented to derive the impact of process and design parameters on 1/f and thermal noise for a low noise CIS readout chain. It is shown that dramatic noise reduction is obtained by using a thin oxide transistor as the source follower of a typical 4T pixel. This approach is confirmed by a test chip designed in a 180nm CIS CMOS process, and embedding small arrays of the proposed new pixels together with state-of-the-art 4T pixels for comparison. The new pixels feature a pitch of 7.5µm and a fill factor of 66%. A 0.4e-RMS input-referred noise and a 185µV/econversion gain are obtained. Compared to state-of-the-art pixels, also present onto the test chip, the RMS noise is divided by more than 2 and the conversion gain is multiplied by 2.2.

A sub-0.5 e − rms temporal read noise VGA (640H×480V) CMOS image sensor has been integrated in a standard 0.18 µm 4PM CMOS process. The low noise performance is achieved exclusively through circuit optimization without any process refinements. The presented imager relies on a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. With a pixel bias of 1.5 µA the sensor chip features an input-referred noise histogram from 0.25 e − rms to a few e − rms peaking at 0.48 e − rms. The imager features a full well capacity of 6400 e − and its frame rate can go up to 80 fps. It also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e − /s. It is also shown that the implementation of the in-pixel n-well does not impact the quantum efficiency of the pinned photo-diode.