Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips -3D Stacked ICs -there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.Publisher's Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Breeta SenGupta received her M.Sc. degree from Indian Institute of Technology, Kharagpur, India, in 2009. She pursues her Ph.D. at the Department of Electrical and Information Technology, Lund University, Sweden. Her area of research includes 3D integration and testing. Breeta is currently engaged in development and verification of RF ASIC at Ericsson, Sweden.