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Have you ever had the problem of trying to determine what compression technique to use from which tool vendor and what to do if any of that changes during the design flow?This paper will present a DFT architecture and automation solution that provides flexibility for designs using scan compression.It combines generic and proprietary techniques to enhance testability, reduce design risk, and improve development time.Data and results for the use of this technique in a microprocessor chip will also be presented.

In general, scan shift failures are difficult to debug. Usually we use the compressed-mode chain test or scan capture-based chain diagnosis to ascertain the small chain segment or the position of the sequential element in the chain that is the cause of the failure. This method of diagnosis works well when the failures are static and limited to a chain segment, but fails to give results when the failure is caused by intra chain or inter chain segment interactions. This paper presents a scenario in which the root cause of the chain failures was due to interaction between chains. We call it the “invisible flaky chain defect” because -- although we were able to replicate failure at a test point (voltage-frequency) on the Shmoo -- the failing cycles changed from run to run.