We present here Transproc, a reconfigurable generic processor which can execute operations related to linear transformations like FFT, FDCT or FDWT. A graph theoretic lemma is used to find the applicability of such a processor to calculate the flow graph related parallel operations found in these linear transformations. The architecture level design and processing element level design is presented. The primitive instruction set and the control signal implementing the instruction set is proposed. A detailed simulation validating the correctness of PE level and the architecture level data calculation and routing operations are carried out using Xilinx Vivado Webpack. The result related to size, power and timing requirement is presented.

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A reconfigurable transform processor is proposed and implemented here. Firstly, a brief study of processors implementing different transformations is presented. We have categorized the transform processor as the one which can implement a number of linear transforms using reconfigurability. The theoretical suitability regarding the architecture of the processor is proved by graph theory method. Then the complete architecture of the overall processor and the processing element is presented and implemented using VHDL. The complete instruction set suitable to the processor is designed. The instructions are mapped to the sequence of control signals. Generating sequence of control signals for every type of instructions would finally create a hardwired control unit for the processor which was also presented. Next the processor is fed with data to simulate it. A three-phase simulation is carried out to prove the correctness of the design. Finally the same processor with a data bus width of 32 to 512 is implemented and compared in terms of speed and size.

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