No abstract

Objective: This paper introduces the computationally efficient, low power, high speed partial reconfigurable Finite impulse response (FIR) filter design using multiple constant multiplication technique (MCM). The complexity of many digital signal processing (DSP) systems is reduced by multiple constant multiplication operation.Methods: Multiple constant multiplications (MCM) along with methods like common sub expression elimination (CSE) is used for the better performance of digital signal processing systems. This paper introduces a CSE operation of finite Impulse response filter design which is solved with decreased number of operators.Results: Using these techniques shows that the area efficiency is increased when compared with designs based on direct form implementation of FIR filters. Conclusion:This method has achieved minimum area and delay with a high process rate. The future work will be for using CSE for 0-1 ILP.

Fast Fourier transform (FFT) is one of the most important tools in digital signal processing as well as communication system because transforming time domain to S-plane is very convenient using FFT. As FFT uses various techniques to convert a signal from time domain to S-domain and inverse, out of which butterfly technique is the one on which paper is focused on. Butterfly technique uses additions and multiplications of operands to get the required output. Floating point (FP) is used as operands due to their flexibility. As the computations involving FP has less speed, we have used binary signed digit (BSD). BSD will take the less time for addition and subtraction. Three bit BSD adder and FP adder together will make a fused dot product add (FDPA) unit. In FDPA, unit addition and subtraction will be one group and multiplication will be one group and then their respective results will be fused. Modified booth encoding and decoding algorithm are used here to make the complex multiplication with ease.