Due to the increasingly critical role played by yield performance in VLSI device market competition, the development of yield models for product design and production control and improvement is nowadays a very active field of research and development. The overall manufacturing yield can be decomposed in several yield contributions related to different phases of the production process or to different degradation mechanisms. Defect yield losses are related to local device deformations usually due to spot defects and particles. Parametric yield losses are linked 10 global device deformations related to limited control on process conditions. In the paper several state‐of‐the‐art modeling approaches to these yield terms will be presented. Moreover, the issue of yield control and monitoring for each of these loss contributions will be reviewed.