Implementing efficient and cost-effective power regulation schemes for battery-powered mixed-signal SoCs is a key focus in integrated circuit design. This paper presents a fully-integrated switched-capacitor DC-DC converter in 45 nm digital CMOS technology. The proposed implementation uses digital capacitance modulation instead of traditional PFM and PWM control methods to maintain regulation against load current changes. This technique preserves constant frequency switching while also scaling switching and bottom-plate losses with changes in load current. Therefore, high efficiency can be achieved across different load current levels while maintaining a predictable switching noise behavior. The converter occupies only 0.16 mm 2 , and operates from 1.8 V input. It delivers a programmable sub-1 V power supply with efficiency as high as 69% and load current between 100 A and 8 mA. Measurement results confirm the theoretical basis of the proposed design.

The dual-frequency single-inductor multiple-output (DF-SIMO) buck converter topology is proposed. Unlike conventional single-frequency SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency ( 2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A low-power 5-output 2 MHz/120 MHz design in 45 nm with 1.8 V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 V to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10 µH off-chip inductor, 2 nF on-chip capacitor for each 15 mA output and 4.5 nF for the 50 mA output. The peak efficiency is 73%, dynamic voltage scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-regulation transients.Index Terms-Dynamic voltage scaling, inductor-based power converters, integrated DC-DC power converters, power management, SIMO power converters.

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TXReducing power consumption through V DD scaling is a major trend in nanometer CMOS circuits. In modern wireless SoCs, multiple power domains operate below 1.2V and draw less than 10mA of current. Currently, these domains are powered from a 1.8V rail through a low drop-out linear regulator (LDO). The 1.8V rail is obtained from a Li-ion battery using a switching regulator with offchip passives. It is highly inefficient to power circuit blocks that operate below 1.2V through LDOs. Switched-capacitor (SC) DC-DC converters are a viable solution to replace LDOs in some on-chip power domains but they currently occupy a large on-chip area [1]. Also, the voltage regulation schemes employed by current SC converters are either unsuitable in wireless systems or do not provide high efficiencies in on-chip use cases due to the dominance of bottom-plate and switching losses [2]. In this paper, a completely on-chip SC DC-DC converter that uses a digital capacitance modulation scheme to achieve voltage regulation is presented. The converter occupies only 0.16mm 2 in total area and provides up to 8mA of current to output voltages between 0.8V to 1V from a 1.8V input while switching at 30MHz. Figure 10.7.1 shows the G2BY3 gain setting (gain of 2/3) used to deliver load voltages between 0.8V to 1V. The signals φ 1 and φ 2 are non-overlapping phases of a clock switching at frequency f s . The circuit is two-way interleaved to reduce input current and output voltage ripple. The load current handling capability [2] of the G2BY3 gain setting is given bywhere 64C B is the total on-chip charge-transfer capacitance used, Q L is the charge delivered to the load every switching cycle and I L is the current delivered at the load voltage of V L . It can be observed from Eq. (1) that in order to regulate the output to a specified voltage V L while delivering a load current I L , the only available knobs are f s or Q L . Pulse frequency-modulation (PFM) [2] schemes change f s to maintain regulation. While this is useful in certain digital systems, in wireless systems, where the digital load being supplied co-exists with critical analog/RF blocks, tones that cover a wide frequency range are challenging (if not impossible) to handle. Hence, a constant frequency regulation scheme is required. Constant frequency control methods often use duty cycle [1] or segmented switch width [3] modes of control to change Q L . These control schemes do not scale switching and/or bottom-plate losses with change in load current leading to a drop in efficiency at low loads. Also, effective regulation with a wide change in load current is difficult to achieve with the abovementioned methods especially when taking process variations into account.To overcome these problems, a digital-capacitance-modulation (DCM) mode of control is introduced, where regulation is maintained by controlling the amount of capacitance that takes part in the charge transfer process. Figure 10.7.2 shows how the capacitors are partitioned for one tile of the interleaved structure. The charge...

An analog adaptive equalizer based on a feed-forward architecture is implemented in 0.18-m digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125 Mbps over Unshielded-Twisted-Pair Category-5 cable of up to 100 m. Novel low-power circuit and system techniques resulted in 3.7-mW total power consumption and supply voltage operation as low as 1.6 V. The maximum peak-to-peak jitter at the output of the equalizer (including the transmit path driver) under all cable length is 0.33 UI. The total area of the equalizer is 27738 m 2 .