It is an important and challenging task to develop concepts and skills of undergraduate engineering students in computer programming course and hence their evaluation on higher order skills. Already several methods are developed to evaluate the students of this course for various engineering programs, but a method for undergraduate electrical and electronic engineering (EEE) program was not found in the literature. In this paper, a simple evaluation method for the students of computer programming course of undergraduate EEE (BSc in EEE) program has been reported using result-oriented learning. Detail methodology, course syllabus design, course outcomes (COs) and mapping it with program outcomes (POs) of BSc in EEE, question setting following Bloom’s taxonomy, laboratory experiment, assessment plan, course and PO evaluation data and graphs have been presented along with relevant statistics. All data are presented for a cohort of students who took this course in summer 2019 Semester at EEE Department of Southeast University. It has been observed that the target set by the course teacher has been achieved by the students. Recommendations of the course teacher for further improvement of the COs’ achievement have also been presented. Keywords: CO evaluation, programming course, OBE

In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.