The contact resistance between TiSij and shallow n'^/p'^ source-drains in CMOS is studied for a variety of junction depths and silicide thicknesses. The contact contribution to the total device series resistance can be significant if excessive silicon and dopants are consumed during silicide formation. Low contact resistances are obtained for 0.15-/im n"^ and 0.20-/im p*^ junctions when the titanium thickness is reduced to keep a high doping concentration at the TiSij/Si interface. Alternatively, a nonstandard process can be employed to implant additional dopants into the titanium. A thin layer of dopants then outdiffuses into the silicon after the silicide reaction and anneal to help reduce contact resistance ^Copyright 1987 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor. and leakage currents. The latter technique is more extendable to CMOS devices which require thicker titanium films and/or shallower junctions.