Intel Corporation a-CH5-157 / b-CH5-148 5000, W. Chandler Blvd. Chandler, AZ Peripheral array BGA with 800x800 mils die on a 42.5x42.5 mm OLGA 'I7] package mounted on FR4 substrate. Peripheral array BGA with 717x604 mils die on a 42.5x42.5 mm OLGA [I7] package mounted on FR4 substrate. Full grid array BGA with 400x400 mil die on a 32x32 mm OLGA "' I package mounted on FR4 substrate. Full grid array BGA with 800x800 mils die on a 42.5x42.5 mm OLGA [17] package mounted on FR4 substrate.Abstract agreement explaining the crack location, propagation and Ball Grid Array (BGA) is currently the interconnect of crack lengths. choice for attaching microprocessors on a printed circuit Based on this data, the effect of package design board (PCB). The reliability of solder joints is one of the parameters on the propensity of BGA fatigue failure are critical issues in BGA surface mount technology (SMT). predicted, and recommendations are made for future package During reliability testing, BGA fatigue failures were designs. Furthermore, the identified maximum damage observed on test vehicles (TV). Finite element analysis and accumulation locations for different BGA patterns provides physical failure analysis were used to determine the risk to the product in the field. As part of this effort, parametric finite element analysis was carried out to determine the effect of design features like the package size, and BGA pattern on the propensity of fatigue failure. The results of the finite element analysis and physical failure analysis showed that the risk to fatigue failure was much greater on a peripheral / partial grid array package than in a full grid array package.

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Far infra-red Fizeau interferometry and shadow moire with enhanced sensitivity are described as tools for warpage measurement of electronics devices. The methods are implemented by develolping a compact apparatus that combines the two methods to provide a capability of thermally-induced warpage measurement with a variable sensitivity ranging from 2.5 pm to 100 pm. The apparatus is based on a computer controlled environmental chamber, which allows real-time measurement during thermal cycling. Selected applications of IPBGA packages are presented to demonstrate its capability. The technique offers a unique capability of accurate documentation of warpage, which leads to precise assessment of package performance and thus helps optimize package reliability and manufacturing process at the early stage of product development.

Integrating a low-K ILD layer within silicon is key to reducing RC delays. However, low-K ILD materials typically have low mechanical strength, making their incorporation with lead free interconnects an industry-wide challenge. It is well known that conversion to lead free first level interconnects increases die backend stresses due to the higher melting temperature and increased solder stiffness. The paper will focus on the measurement of the effective silicon backend strength after subjecting the dice to different fabrication and assembly steps. The effective strength will also be evaluated post reliability stress exposure to eventually understand the life of these films. The paper will describe how a commercially available Dage 4000 tool was modified for this application. Bump pull was carried out using a 100μm tweezers, while bump shear used 1mil (25.4μm) wide stylus. Static and dynamic calibration was first carried out to ensure repeatability and reproducibility of the results. Peak force and failure modes were used as metrics to compare the effectiveness of different experimental legs. Traditional failure analysis approach of mechanical polishing, or when needed, use of FIB for sample preparation, with subsequent SEM/EDX analysis was utilized to understand the failure mechanism. Data suggests that shear and pull lead to different failure modes. Bump shear mainly led to failure at the bump/polyimide interface and did not necessarily correspond to the weakest layer or interface in the silicon backend. Whereas bump-pull, which applies tensile force to the stack up, lead to failures in the weakest layer, typically the low-K ILD, in the silicon backend. Hence, bump pull provided the advantage over shear as it allowed evaluation of the weakest interface in the stack up. Two case studies are discussed to demonstrate on how bump pull/shear metrologies were used to understand the impact of different assembly/FAB process variables and highly accelerated steam test (HAST) reliability stress on silicon backend strength. First case study shows influence of assembly flux on silicon backend strength, while second case study describes impact of HAST on different FAB backend processes.

Thermal expanSian mismatch between electronic devices and their substrates induces stresses in the assembly during bonding and operation. These stresses in extreme cases cause cracking of the electronic device during bonding. For GaAs devices back-side bonded to a high conductivity artificial diamond substrate using Au-Sn solder, analytical and numerical analyses were conducted to determine the bonding stresses in the GaAs die. Bonding et s were conducted to study the effect of varying cooling rates on die failure. Experimental data demonstrate that only smaller sized dice (lmm X lmm and 2mm X 2") survived bonding without cracking. This observation was corroborated by analfical and numerical studies which show that the stress induced in the larger dice exceeded the strength of the material. Slow ("2 T/min) but continuous cooling from the bonding temperature did not improve the survival rate of the dice si@icantly. A new cooling scheme was developed utilizing the high temperature creep properties of the Au-Sn solder. This cooling scheme incorpora solder layer creep at high temperatures to relieve the stresses in the attached die. Bonding experiments with sizes up to 1 0 " X l o " and thicknesses down to 4 mils were performed with a 100% survival rate of the dice. Introduction:To meet the demand for higher performance microelectronics,