In this paper, we describe the challenging first-and secondlevel packaging technology of a new system packaging architecture for the IBM eServer z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

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This paper describes an efficient methodology for mid-frequency delta-I noise analysis of the power distribution network of a computer system. The method allows fast and accurate power noise simulations with SPEED97 on highly complex packaging structures. Simulation results for the mid-frequency power noise amplitudes on module and board planes and dependencies on decoupling capacitor parameters are presented. The package model used for the simulations allow the identification of the dominant resonant oscillations on the power distribution system following a delta-I step and yield the time response of the on-chip, on-module and on-board decoupling capacitors. The simulation results have been confirmed by measurements within 5%.

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