This paper proposes an optimized Multi-Level Inverter (MLI) topology with symmetrical and asymmetrical DC sources for sustainable energy applications. The proposed MLI has optimized components to reduce size, cost, and installation area in comparison with traditional MLIs. It also improves output power quality by reducing harmonics in the stepped output, and hence it can be used for sustainable energy applications with a grid interface. The proposed inverter is equipped with six switching devices, one clamping diode, and two DC sources. It produces a five-level stepped output when using symmetrical DC sources and a seven-level stepped output when using asymmetrical DC sources. In this topology, the six switching devices are divided into two units, namely the level generator and the polarity generator units, the switches used in the level generator are responsible for producing the required number of levels in the form of rectified stepped output and the switches used in the polarity generator are responsible for converting the rectified stepped waveform to stepped AC output. The simulation results verify the operation of the MLI when fed with linear load with symmetrical and asymmetrical DC sources, and the experimental output results are presented for validation.

This paper presents a single-phase seven level Cascaded H-Bridge DC-Link (CHBDCL) inverter for marine electric propulsion drives. The speed of propulsion drive can be changed by CHBDCL inverter by converting DC output from the rectifier to variable output voltage with or without change in frequency. The proposed CHBDCL inverter generates more output voltage with minimum harmonic content than classical Multilevel Inverters (MLIs). The CHBDCL inverter necessitates only ‘m + 3’ power devices for ‘m’ number of levels, although the classical MLIs requires ‘(2m − 1)’ power devices. CHBDCL inverter can have the effective performance by utilizing unipolar Sine Pulse Width Modulation (SPWM) and unipolar Space Vector PWM (SVPWM) with sine carrier. The effectiveness of the proposed CHBDCL inverter topology has been verified by using MATLAB/SIMULINK for various modulation indices in terms of voltage levels and harmonic analysis. Furthermore, an experimental setup involving pulse generation from a Field Programmable Gate Array (FPGA) has been used to test the performance of the proposed CHBDCL inverter.

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In this paper, advanced DC-Link (DCL) based reversing voltage type Multilevel Inverter (MLI) topologies by compensating the difficulties in the conventional MLIs are reviewed. These topologies consist of less switching components and driver circuits when compared with conventional MLIs predominantly in higher levels. Consequently, installation area, total cost and hardware difficulties are reduced by increasing the voltage levels. The unipolar based Pulse Width Modulation Schemes (PWMS) will improve DCL inverters performance. This paper presents unipolar Multi-Reference (MR) based sine and space vector PWMS with single triangular carrier wave for generating required levels in output voltage. Comparison between UMR sine and space vector PWMS for DCL inverter topologies is presented in terms of Fundamental Output Voltage (FOV) and Total Harmonic Distortion (THD). The research tries to establish the survey analysis for single-phase 7-level DCL based reversing voltage type MLI topologies with UMR based sine and space vector PWMs. Finally, to confirm the feasibility of proposed DCL-MLIs in terms of FOV and THD the simulation results are incorporated. Further, the prototype model is developed for single-phase 7-level DCL inverter with Field Programmable Gate Array (FPGA) based UMR sine and space vector PWMS to authenticate simulation results. The efficiency of the proposed cascaded MLI achieves the value of 99.003%.

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