Finite Impulse Response (FIR) filter is a major building block in Digital Signal Processing (DSP) system. The conventional FIR filters are implemented by utilizing a normal adder, which consumes more area. Minimizing the hardware utilization of the adder is a significant challenge in FIR filter design. Generally, complexity of the FIR filter is dominated by the adder. So, an efficient FIR filter was designed with the help of Carry Select Adder (CSLA) to reduce area and hardware complexity of the accumulation block. The area has been reduced by using CSLA that is very significant idea while designing a less area filter. The proposed method named as Low Area-CSLA-FIR (LA-CSLA-FIR) filter. The LA-CSLA-FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) on different devices such as Virtex-4, Virtex-5 and Virtex-6 by using Verilog code. The experimental results of the LA-CSLA-FIR filter design reduced average the FPGA device utilization: 15.38 % of LUTs, 8% of flip flops and 8% of slices on Virtex-5 compared to existing filter designs.

Purpose Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization. Design/methodology/approach The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324. Findings The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively. Originality/value The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

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PurposeFinite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs.Design/methodology/approachTo overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices.FindingsThe experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.Originality/valueThe experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.