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We describe the design of a high performance 2 bits per cell Flash memory device capable of 8ns synchronous access rate capable of operation at up to 125MHz in burst mode and asynchronous page mode access rate of 1411s. The device is fabricated on Intel's 0.18pm ETOXTM VI1 Process technology.

Traditional non-volatile flash memories cannot support simultaneous read while write (RWW) i.e. read while pmgramming or erasing the device 111. This shortcoming is addressed by a hardware boundary that divides a flash memory map into 2 elear-eut segments that support simultaneous RWW operations. In this scenario, one segment can be used for the code and the other segment can be used for data. This approach does not allow users to choose the optimal size of the code and data partitions for their particular applications. The use of flash memory as a medium for code+data storage places additional demands on the traditional architecture. The above limitations show the need for truly flexible multi-partition memory architecture.This flash memory is a truly flexible RWW device that allows the memory to be divided into any number of partitions, in this case, each 4Mb, which allows simultaneous RWW operations. This flexible multi-partition architecture allows two processors to interleave code operations while program and erase operations take place in the background. Figure 1 shows the chip plan for the device. The RWW functionality is achieved by separating the write and read paths of the device. The write and read status of each partition is stored in a state machine. The user changes the write and read status by issuing commands to the device. Figure 2.3.1 also shows some of the possible RWW scenarios for the device in a tabular format. The device allows reads in one partition whilk writing in another partition. As shown in Figure 1, the device is partitioned into 16 4Mb partitions. Far example, the user may start a write operation in one of the 16 partitions and while the device is writing to that partition, the user can read the array, the signature or the status in any of the other 15 partitions. Figure 2.3.2 shows waveforms of a read while programming operation where a selected wordline and hitline are a t program voltages in one partition while another set of selected wardline and bitline are a t read voltages in another partition. This example illustrates the full capability of a truly flexible RWW architecture in which a user can seamlessly access data across various partition boundaries.The device provides a n initial access time of 40ns for the first word followed by l0ns access time for the subsequent words in its default four-word page made. This results in an average asynchmnous access time of 18ns per word. 18ns is achieved using address transition detection (ATD) to control the entire read operation. The sensing architecture works with a two-stage dynamic latch-type sense amplifier. Figure 2.3.3 shows the RWW sensing architecture. Figure 2.3.4 shows a dctailed implementation of the sensing architecture. Refer to Figure 2.3.5 for the following read operation example. After an address transition is detected a t T1, a n initial master pulse begins the read cycle. Subsequent pulses enable each stage of the read circuits. The first pulse enables the ward line a t n. The second pulse connects the bit lines t...

In flash memory designs, the speed of program performance is very critical in many applications. To improve program performance, more memory cells must be programmed in parallel. In a typical system, only 1.8V is available for a flash device that requires 6V at a high current for programming. In the traditional scheme, capacitive charge pumps are used for the generation of voltages higher than the external power supply. If capacitive charge pump schemes are used to program more cells in parallel, they become prohibitive in terms of die area and power. In the design reported in this paper, an inductive reactance is used to boost the supply voltage and transfer the energy to a capacitor. The unique feature of this design is that a discrete inductor is incorporated inside the package and bonded on top of the flash die while the control circuitry is integrated into the flash silicon. This design offers die size savings and lower power consumption over the traditional method. A significant improvement in NOR flash write performance is realized when implementing this scheme.As the supply voltage scales down, the numbers of stages in the capacitive charge pumps increase and the capacitors need to be upsized to obtain the same output voltage and currents. This has an impact on the die size as each of the capacitors in the pump cell consumes substantial silicon area. Also, the output current and power efficiency in capacitive charge pumps are limited by the inherent power losses associated with the switched capacitor booster. This overhead in area and power of the capacitive charge pumps limits the programming performance of the NOR flash memory devices. A typical 1.8V NOR flash memory device using capacitive charge pumps may program only 2 to 4 cells in parallel limiting the program performance to 0.2MB/s. The 128Mb flash memory device described in this paper presents an alternate solution to generate high voltage using an inductive booster pump. Figure 2.4.1 shows the chip plan for this 128Mb NOR flash memory device consisting of 32 4Mb flash memoryarray partitions and on-chip control circuitry for the inductive booster. The salient feature of this design is that the inductor is located external to the silicon but inside the same package so that it is transparent to the user. No extra pins are required and significant silicon area is saved. The inductive booster pump offers much higher power efficiency, on the order of 85%, compared to 20% for the conventional capacitive charge pump. This inductive booster converter programs 16 to 32 flash cells in parallel with fast pump slew times at a write performance rate of 3MB/s. The program current of this device is about 21mA which represents a savings of 48mA over a comparable design using capacitive charge pumps. Figure 2.4.2 describes the architecture of this 128Mb NOR flash memory device. This includes an inductor booster converter that operates from a 1.8V supply and generates 4-12V at its output. This output drives the flash array drain path during program operation and d...