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Using an Al/SiO 2 ͑wet͒/Si 0.9 Ge 0.1 /n -Si/Al capacitor structure, effects of oxidation on bulk trap and interface states near the SiO 2 /SiGe interface are investigated. Two peaks at the energy levels of 0.23 eV (D1) and 0.40 eV (D2) below the conduction band edge are observed with the capacitance deep level transient spectroscopy ͑DLTS͒ method. The DLTS measurement results show a characteristic feature of interface states for the D1 peak. The interface state distribution obtained by the capacitance-voltage method also has a high density (6.9ϫ10 12 /cm 2 eV) peak at an energy level of 0.23 eV below the conduction band edge. The Si-O-dangling bonds are thought to be the source of the D1 peak. The annealing behaviors of the D2 peak show that D2 is a divacancy related bulk trap. The capture cross section and the trap density for the bulk trap D2 are 2.06ϫ10 Ϫ15 /cm 2 and 1.8ϫ10 14 /cm 3 , respectively. The density of D2 is significantly reduced after low temperature postmetallization annealing.

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S parameters for eliminating deembedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S parameters from 0.1 to 26.5 GHz.

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