 Abstract: Now the era is of electronic gadgets like processors and portable devices, in which Memory plays a significant role through the usage of Static RAMs (SRAMs).Hence designing of Low power SRAM is immense for applications. But the design of SRAM is involved in higher power requirement. So there is still scope for adequate Low power Memory Array design. The Main Moto of this paper is involved in designing & Simulating Low Power 16x16 SRAM Arrays using 7T SRAM cells based on Conventional, Self Controllable Voltage (SVL) & Improved Self Controllable Voltage (I-SVL) methods. Also Comparative Power and SNM Analysis is carried between Conventional 7T, 7T-SVL and 7T-ISVL based Arrays. The Proposed Array using 7T Cell consumes 6.24mW which is 67.64% lesser than the Array design [2].Also I-SVL based 7T SNM is better than the SVL-7T and 7T based cell.The proposed work is carried using cadence virtuoso tool with standard library gpdk 180nm.Also Proposed Array based on I-SVL is efficient in terms of power. The proposed Cell SNM resulted in 68.57% higher in comparison with existing cell of 8T and 10T [3].