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This paper describes the design of a 64-processor by 128-memory CMOS crossbar switching network that establishes working performance and density limits for a medium-scale ideal network. The design is based on advanced packaging technology employing tape-automated bonding (TAB) of integrated circuit components io 3.2Y-square high-density interconnect substrates. The entire electronics for 64 32-bit processors, their caches and network interfaces. the crossbar network, and 128 memory units with associated memory controllers fit within the dimensions of a shoebox. The maximum available data transfer bandwidth is 51.2 Gbitls. Minimum end-to-end latency to read a 40-bit memory word is 450 ns, while minimum write latency is 300 ns. The expected end-to-end latencies after correcting for contention (assuming uniform access probabilities) are 570 ns and 380 ns, respectively, for the cuse that all memory accesses go through the network (caching turned off). Our design reveals the critical impact of network control (especiully request arbitration) on the performance and efficiency of [he entire system. -PO

No abstract