Carbon-based sensors are attractive because of their excellent sensing capability. In this paper, we propose a new approach to analytically model the sensitivity of these devices based on graphene. The model relies on the surface potential and current of the device. For the first time, we included ionization in the modelling and examined the importance of this effect. In order to validate the model, the results are compared with experimental data from a fabricated device.

In this paper, a new analytical approach is presented to study the effect of commonly used topologies on the energy consumption and delay of on chip network (NOC) testing using IEEE 1149.1 standard. Here, first we model the energy of each module in JTAG standard, and then using test access port (TAP) controller state diagram and test algorithm, the totoal energy based on each topology is calculated. In addition, the number of clocks is calculated and together with the propagation delay of basic gates, the test time is modelled and calculated. Using the results we can choose the least energyconsuming and fastet topology in terms of testing. The modelling is verified using FPGA implementation.