In this paper, the algorithm of a VLC codec system with new group-based approach is presented. Based on the proposed codeword grouping and symbol memory mapping, the groupsearching scheme and codec processes are completed by applying numerical properties and arithmetic operations to codewords and symbol addresses. The memory requirement of encoder is reduced by a novel symbol-converting scheme. Therefore, the programmable coding table and symbol representation can be achieved. Based on MPEG-like systems, an architecture design that performs concurrent VLC codec processes with constant symbol rate is presented. Simulation results show IOOMsps with 100MHz-clock for both encodingldecoding procedures can be achieved. As a result, it is suitable for those applications that require codec processes simultaneously, such as videoconferencing, and high throughput systems, such as HDTV. IntroductionRecently, progressive applications, such as HDTV, videoconferencing and user-defined coding table system, make challenges to VLC codec technology. The compressed bit stream of HDTV system is more than IOOMbps since the sampling rate is about 52Mpixelhec and the color profile is 4:2:2. Subsequently, the throughput requirement of VLC codec operation is increased several order of magnitudes than earlier applications. In contrast, the bit rate is much lower for videoconferencing which is established on the limited network bandwidth. However, the 2-way communication needs real time concurrent encodingldecoding procedures. To meet diverse applications and different data types, user-defined coding tables that are generated by precise symbol probability are essential to hrther increase compression ratio. Because the table information has to be loaded before the codec processes, the VLC codec systems require the programmability to change coding table without redesign.Both tree-searching and group-based algorithms for VLC codec system have been discussed. By representing coding To satisfy the mentioned application, the motivation behind our research is to develop a programmable coding table, low memory requirement, and high throughput VLC codec system. A new group-based VLC codec algorithm which take the advantage of numerical property of codeword and symbol address are presented. The operation throughput is improved significantly. With memory-based architecture, coding tables and symbol representations can be programmed. The organization of this paper is as follows. In section 2, the group-based VLC encodingldecoding algorithm is described. The symbolconverting scheme is presented, too. In section 3, the VLC codec architecture and performance estimation is discussed. Finally, concluding remarks are made in section 4.

In this paper, we propose an adaptive and scalable soft variable length code (VLC) decoder to greatly reduce overall design complexity. Generally, a soft VLC decoder needs to maintain many states for the correct decoding when the sequence length or table size grows. We propose an adaptive sorting scheme to reduce the memory accesses and design complexity. We reduce the table size by using symbol-merging and table-merging schemes. In addition, the proposed Black-Box model improves the accuracy of performance estimation by a novel measurement of "symbolalias" and also achieves a better tradeoff between performance and complexity. Further, no side information is transmitted and the proposed soft VLC decoder is bandwidth-efficient. The proposed design is evaluated using the model of MPEG-4/UDP-Lite/UEP/ AWGN, and hence it is standard-compliant. We averagely improve the peak signal-to-noise ratio by 0.4 2.9 dB as compared with traditional VLC decoding and standard-support reversible VLC decoding schemes.

In this paper, a low power variable length code decoder with group-based scheme [10] is proposed. It can save at most 70% power dissipation while maintaining the same throughput rate as the conventional one. This proposal mainly consists of look-up table (LUT) partitioning and group-based memory storing, where the former is used to reduce the power wasted on lookingup unnecessary code-words due to a large LUT, especially those code-words with low probability; the latter is used to reduce the storage space of VLC tables and maintain the flexibility of our hardware decoder.

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A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-m CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock rate f f f clock ; and 3) the function of nonreturn-to-zero clock recovery has a maximum f f f clock /4 recovering capability with a locking range of (input 6 6 6 input /2), where input is the input period.