The testing of cyber-physical systems requires validating device functionality for a wide range of operating conditions. The environment with which the cyber-physical device interacts, such as lungs for a medical ventilator device or a busy freeway for an autonomous vehicle, may be complex and subsequently difficult to explore all possible configurations. Computer simulations that utilize device and environment behavioral models may be used as a first stage of testing, but at some point development must occur using the real device running in real-time. We present a codesign framework for aiding cyber-physical device development where real devices or prototypes are connected to real-time models that simulate the interacting environment. Such test setups are known as digital mockups and allow for testing environment scenarios that are hard to capture with commonly-used but limited physical mockups. The framework supports model hardware/software codesign to enable models of varying speed and accuracy to be implemented within an embedded processor or as a custom coprocessor circuit on an FPGA. We describe an accompanying tool that generates code templates to reduce the time required to develop digital mockup test setups. We utilize the framework to build a digital mockup test setup for a commercial ventilator, and showcase codesign capabilities by implementing environmental models as both circuits and as instructions on a processor.

Physical system models that consist of thousands of ordinary differential equations can be synthesized to field-programmable gate arrays (FPGAs) for highly-parallelized, real-time physical system emulation. Previous work introduced synthesis of custom networks of homogeneous processing elements, consisting of processing elements that are either all general differential equation solvers or are all custom solvers tailored to solve specific equations. However, a complex physical system model may contain different types of equations such that using only general solvers or only custom solvers does not provide all of the possible speedup. We introduce methods to synthesize a custom network of heterogeneous processing elements for emulating physical systems, where each element is either a general or custom differential equation solver. We show average speedups of 45x over a 3 GHz single-core desktop processor, and of 11x and 20x over a 3 GHz four-core desktop and a 763 MHz NVIDIA graphical processing unit, respectively. Compared to a commercial high-level synthesis tool including regularity extraction, the networks of heterogeneous processing elements were on average 10.8x faster. Compared to homogeneous networks of general and single-type custom processing elements, heterogeneous networks were on average 7x and 6x faster, respectively.

Medical devices have become more difficult to test as hardware and software complexity grows. Device manufacturers must meet minimum standards while striving to reduce product development time. New techniques for providing comprehensive testing need to be developed that can be easily configured, cover a broad range of test scenarios, and facilitate automation. Digital mockups describe a method of testing a cyber-physical device wherein a digital model of the environment is used to stress a real device's embedded software and functionality. We demonstrate the use of a digital mockup to test a medical ventilator device. A lung model is hosted on an FPGA and connected to a ventilator by bypassing the ventilator's transducers. PC-based manager software allows user configuration in real-time of both the device and the model to facilitate test automation. An XML model description is embedded in the digital mockup framework to facilitate communication between the FPGA and PC software.

RIOS (Riverside-Irvine Operating System) is a lightweight portable task scheduler written entirely in C. The scheduler consists of just a few dozens lines of code, intended to be understandable by students learning embedded systems programming. Non-preemptive and preemptive scheduler versions exist. Compared to the existing open-source solutions FreeRTOS and AtomThreads, RIOS on average has 95% fewer lines of total C code for a sample multitasking application, a 71% smaller executable, and 70% less scheduler time overhead. RIOS source code and examples are available for free at http://www.riosscheduler.org. RIOS is useful for education and as a stepping stone to understanding real-time operating system behavior. Additionally, RIOS is a sufficient real-time scheduling solution for various commercial applications.

Emulating a physical system in real-time or faster has numerous applications in cyber-physical system design and deployment. For example, testing of a cyber-device's software (e.g., a medical ventilator) can be done via interaction with a real-time digital emulation of the target physical system (e.g., a human's respiratory system). Physical system emulation typically involves iteratively solving thousands of ordinary differential equations (ODEs) that model the physical system. We describe an approach that creates custom processing elements (PEs) specialized to the ODEs of a particular model while maintaining some programmability, targeting implementation on field-programmable gate arrays (FPGAs). We detail the PE micro-architecture and accompanying automated compilation and synthesis techniques. Furthermore, we describe our efforts to use a high-level synthesis approach that incorporates regularity extraction techniques as an alternative FPGA-based solution, and also describe an approach using graphics processing units (GPUs). We perform experiments with five models: a Weibel lung model, a Lutchen lung model, an atrial heart model, a neuron model, and a wave model; each model consists of several thousand ODEs and targets a Xilinx Virtex 6 FPGA. Results of the experiments show that the custom PE approach achieves 4X-9X speedups (average 6.7X) versus our previous general ODE-solver PE approach, and 7X-10X speedups (average 8.7X) versus highlevel synthesis, while using approximately the same or fewer FPGA resources. Furthermore, the approach achieves speedups of 18X-32X (average 26X) versus an Nvidia GTX 460 GPU, and average speedups of more than 100X compared to a six-core TI DSP processor or a four-core ARM processor, and 24X versus an Intel I7 quad core processor running at 3.06 GHz. While an FPGA implementation costs about 3X-5X more than the non-FPGA approaches, a speedup/dollar analysis shows 10X improvement versus the next best approach, with the trend of decreasing FPGA costs improving speedup/dollar in the future.