The current paper deals with limited-budget output consensus for descriptor multiagent systems with two types of switching communication topologies; that is, switching connected ones and jointly connected ones. Firstly, a singular dynamic output feedback control protocol with switching communication topologies is proposed on the basis of the observable decomposition, where an energy constraint is involved and protocol states of neighboring agents are utilized to derive a new twostep design approach of gain matrices. Then, limited-budget output consensus problems are transformed into asymptotic stability ones and a valid candidate of the output consensus function is determined. Furthermore, sufficient conditions for limited-budget output consensus design for two types of switching communication topologies are proposed, respectively. Finally, two numerical simulations are shown to demonstrate theoretical conclusions.Index Terms-Multiagent system, descriptor system, output consensus, limited budget, switching topology. I. INTRODUCTION D URING the last decade, consensus of multiagent systems receives considerable attention, which designs a distributed control protocol to drive multiple agents to achieve an agreement about some interested variables such as time, position, velocity and temperature, et al., as shown in [1]-[6]. Consensus has potential practical applications in formation control [7]-[10], target tracking [11]-[12], network synchronisation [13]-[14] and multiple source data analysis [15]-[16], et al.The communication topologies are critically important for multiagent systems to achieve consensus, which can usually be categorized into the fixed ones and switching ones. For fixed communication topologies, the neighboring relationship and communication weights are time-invariant, as discussed in [17] and [18]. For switching communication topologies, the neighboring relationships may be time-varying, but communication weights are time-invariant. In this case, the associated Laplacian matrices of the communication topologies are piecewise continuous, as shown in [19]-[21], where switching communication topologies are divided into switching connected ones and jointly connected ones. For switching connected communication topologies, each topology in the switching set is connected. For jointly connected communication topologies, the union of topologies in certain time interval is connected, but each topology in the switching set can be unconnected. It is well-known that consensus for jointly connected communication topology cases is more complex than the one for switching connected communication topology cases.

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Fully homomorphic encryption (FHE) allows arbitrary computation on encrypted data and has great potential in privacy-preserving cloud computing and securely outsource computational tasks. However, the excessive computation complexity is the key limitation that restricting the practical application of FHE. In this paper we proposed a FPGA-based high parallelism architecture to accelerate the FHE schemes based on the ring learning with errors (RLWE) problem, specifically, we presented a fast implementation of leveled fully homomorphic encryption scheme BGV. In order to reduce the computation latency and improve the performance, we applied both circuit-level and block-level pipeline strategies to improve clock frequency, and as a result, enhance the processing speed of polynomial multipliers and homomorphic evaluation functions. At the same time, multiple polynomial multipliers and modular reduction units were deployed in parallel to further improve the hardware performance. Finally, we implemented and tested our architecture on a Virtex UltraScale FPGA platform. Runing at 150MHz, our implementation achieved 4.60x~9.49x speedup with respect to the optimized software implementation on Intel i7 processor running at 3.1GHz for homomorphic encryption and decryption, and the throughput was increased by 1.03x~4.64x compared to the hardware implementation of BGV. While compared to the hardware implementation of FV, the throughput of our accelerator also achieved 5.05x and 167.3x speedup for homomorphic addition and homomorphic multiplication operation respectively.

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