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The control of shallow trench isolation (STI) depth uniformity and poly gate profile necessitates the combination of more advanced silicon etch methodologies, in-situ measurements, and various relevant integration schemes. This paper presents a study of the difficulties and corresponding solutions in 65nm silicon etch with respect to process development and mass production. In the development phase, the STI trench profile and the depth uniformity of the STI depth can be well controlled by etch recipe tuning. In the mass production phase, we need to extend additional focus on the impact from different products on the inter-field variation of STI depth. Results show a good correlation of the depth to the pattern density variation. Such relationship has been utilized in feed-forward mode to deliver a robust process control. In addition, we also address the influence of oxide variation in STI fabrication and STI step height difference on the corresponding poly gate profile and the pits defects.

As semiconductor devices are being scaled down to critical dimensions of 65nm and below, the control of the pattern density effect in back end of line (BEOL) etch, in particular the corresponding loading effect, becomes crucial to ensure the on-target production. This paper addresses the challenges and solutions to reduce the influence of pattern density variation in 65nm BEOL logic Al-pad etch processes. Challenges include the impact of pattern density from the corrosion window with different Al-pad photo transmission rates (TR) and the within-wafer profile loading between Al-line (dense feature) and Al-pad (iso feature). Polymer deposition was found to be linked to these issues. The corresponding solutions focus on the adjustment of polymer gas ratio for any product based on its actual pattern density and the optimized combination of etch gases and bias power to reduce the within-wafer dense and iso loading.

In this paper, based on the via-first DD technology, we focus on the profile tuning of via and trench and the liner removal in order to optimize the trench profile. Via profile tuning include how to realize the via with the bowling profile, vertical profile and tapering profile. Trench profile tuning emphasizes the formation mechanism of bowling profile and top rounding profile. Footing profile and under-cutting profile of via bottom in liner open step is also addressed. The effect of different etching profiles on Rc, VBD (Breakdown Voltage) are examined. Results show that different via profiles have no impact on Rc, top-rounding trench-profile results in worse VBD, while under-cut & footing liner would deliver lower and higher Rc, respectively.

This paper presents an effective way to reduce the degradation of the Ring-OSC speed with optimized offset spacer etch, improvement of the within-wafer uniformity of the offset spacer width and the reduction of its profile deviation. We have developed the lower offset spacer etch rate scheme for better control of plasma uniformity in order to achieve the above two targets. Compared with the 3Sigma of 1.3nm offset spacer width uniformity and 1.8nm profile deviation of conventional dielectric etcher with high etch rate, this low etch rate process has delivered the 3sigma of 0.5nm for the offset spacer width uniformity and 0.7nm offset spacer profile deviation. The corresponding Ring-OSC loss has been completely eliminated and the wafer-level yield is enhanced by 40%.