The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instructionlevel parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers. This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multiprocessing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.
Commercial applications such as databases and
Demographic studies were conducted with Lolium rigidum Gaud. growing in winter barley crops at ®ve sites in central and eastern Spain, over a period of 2 or 3 years. Although threefold dierences (34±97%) in annual recruitment were recorded in the various experiments, most of the values were close to the overall average (67%). Seedling emergence took place in a very short period of time after sowing, with 90% emergence generally being reached after a thermal time of 242 d°C (provided soil moisture was adequate at sowing). Seedling survival was very high (78± 95%) in most experiments, with no clear relationship between this parameter and any of the environmental variables studied. Survival curves were relatively linear, with plant mortality increasing gradually throughout the life cycle of the plant. There were 34-fold dierences (from 7 to 237 seeds per plant) in the fecundities recorded in the various experiments. Variation in fecundity resulted partly from dierences in crop and weed densities and total precipitation received during the growth cycle. The annual rate of population growth was estimated based on the above-mentioned parameters. The potential for population growth was high (average k 6.21), but large dierences were obtained for the dierent sites and years.
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